Technical Glossary & Hardware Concepts

Under AAPCS, the first 4 integer or pointer arguments (up to 32 bits each) are passed directly in CPU registers R0–R3 without touching RAM. Return values are passed in R0 (and R1 for 64-bit). The return address is stored in the Link Register (R14/LR). Keeping function parameter counts to 4 or fewer eliminates stack memory push/pop overhead completely.

Enables idiomatic, zero-cost customization points such as swap(a, b) (which selects specialized hardware or container swap functions before falling back to std::swap) and overloaded stream/math operators without requiring explicit namespace prefixes.

Hardware peripherals such as DMA controllers, cache lines (typically 32 or 64 bytes), and vector units require buffers to be placed at specific memory boundaries (e.g. alignas(32) uint8_t dma_buf[512];). Misaligned memory accesses on ARM Cortex-M0/M3 can trigger hardware usage faults or require multi-cycle bus transactions.

In embedded DSP and graphics processing, SoA maximizes cache locality when algorithms only read one or two specific fields across all elements (e.g. updating only X coordinates), enabling contiguous burst reads and SIMD execution without loading unused padding bytes.

Holds the Negative (N), Zero (Z), Carry (C), Overflow (V), and Q (Saturation) flags. Conditional branch instructions (BEQ, BNE, BGT, BLT) directly evaluate these flags to make zero-latency branch decisions. Mispredicting or stalling conditional checks causes CPU pipeline bubbles.

Strictly forbids non-deterministic runtime operations including raw new/delete, dynamic exceptions without bounded catch times, recursion (due to stack overflow risk), and unbounded loops. Mandates static allocation, deterministic response times, and static analysis enforcement.

In Cortex-M3/M4/M7 processors with 3-to-6 stage pipelines, every mispredicted branch incurs a 2-to-5 clock cycle penalty. In high-frequency interrupt service routines (ISRs) and tight DSP loops, branchless code and C++20 [[likely]]/[[unlikely]] annotations eliminate costly pipeline stalls.

The .bss section occupies 0 bytes in Flash ROM storage. During startup before main() runs, the CRT0 startup code zeroes out the entire .bss RAM region in a tight loop. Grouping zero-initialized buffers into .bss saves vital Flash space.

Commonly caused by dereferencing invalid memory addresses, accessing unclocked hardware peripherals (forgetting to enable the APB peripheral clock in RCC registers), or attempting unaligned 32-bit accesses on strict buses. Logged in the BusFault Status Register (BFSR).

When a single byte is accessed, the hardware cache controller loads the entire 32- or 64-byte line. Sequential array traversals exhibit high spatial locality (cache hits), running at ~1 cycle per access. In contrast, linked lists and pointer chasing cause frequent cache misses, stalling the CPU for 10-100+ cycles per dereference.

Precomputing mathematical tables (trigonometric LUTs, CRC tables, state machine transitions) at compile time consumes zero runtime CPU cycles and places the result directly in Flash ROM (.rodata), eliminating RAM consumption and boot-time calculation overhead.

Provides single-cycle or fixed microcode computation of sin(), cos(), atan2(), and polar-to-Cartesian conversions without requiring costly floating-point Taylor series approximations or large RAM lookup tables.

Provides polymorphic interface behavior at compile time without any virtual functions. This completely avoids the VTable and VPtr RAM overhead (saving 4 bytes per object) and enables full function inlining, eliminating indirect jump instruction delays.

Safety standards like ISO 26262 (automotive) and IEC 61508 (industrial) mandate a cyclomatic complexity threshold (typically $\le 10$ to $15$ per function). Lower complexity ensures every branch path can be fully tested with 100% MC/DC (Modified Condition/Decision Coverage) on target hardware.

Requires dual storage: the initial values are stored in non-volatile Flash ROM (LMA - Load Memory Address). At startup, the reset handler copies these values byte-for-byte from Flash into volatile SRAM (VMA - Virtual Memory Address). Minimizing non-const globals directly reduces boot time and SRAM usage.

Allows multi-kilobyte sensor or audio data streams to be received in circular ring buffers in the background while the CPU sleeps in low-power mode (WFI) or executes other real-time tasks. Requires contiguous, properly aligned memory buffers.

Enabling C++ exceptions generates the .eh_frame and .gcc_except_table sections in Flash ROM, causing a 15KB–40KB ROM code size penalty on 32-bit MCUs even if no exception is ever thrown. For this reason, bare-metal systems commonly compile with -fno-exceptions.

Used for persistent configuration parameters, device serial numbers, and calibration offsets. Writes require significant time (3–10ms per byte) and block or require non-blocking I2C/SPI drivers with CRC checks.

ELF files are processed by objcopy to generate flat binary (.bin) or Intel Hex (.hex) files for flashing directly onto physical microcontroller flash memory via JTAG/SWD debuggers.

Avoids quadratic $O(N^2)$ memory copying that occurs when erasing elements individually in a naive loop. In C++20, replaced by the cleaner non-member std::erase(vec, value).

Guarantees zero heap allocation, eliminates memory fragmentation risks, ensures deterministic execution time, and provides MISRA/AUTOSAR compliance for safety-critical real-time applications.

Enables microcontrollers to read and write SD cards, USB drives, and eMMC chips interoperably with PC operating systems (Windows, Linux, macOS) using standard FAT formats.

Provides deterministic $O(1)$ allocation and deallocation without searching or splitting blocks. Completely prevents external memory fragmentation, making it safe for long-running embedded systems.

Flash must be erased in entire sectors or blocks before new data can be written (turning 1s into 0s on write, and resetting to 1s on erase). Write operations are orders of magnitude slower than SRAM and wear down cells over time.

Provides $O(\log N)$ lookup with optimal cache locality because elements are stored contiguously in memory, avoiding the pointer-chasing overhead and 24-byte per-node heap bloat of Red-Black trees (std::map).

Disabling RTTI saves typenames and type descriptors in Flash ROM; disabling exceptions removes .eh_frame tables, reducing overall binary size by 15KB–50KB and ensuring deterministic real-time execution on microcontrollers.

Freestanding C++ requires custom startup code (reset handlers, CRT0), custom linker scripts, and only guarantees access to core language headers (<cstdint>, <cstddef>, <type_traits>, <limits>).

Triggered by null-pointer dereferences, executing invalid opcode bytes, unaligned memory accesses when unaligned traps are enabled, or stack overflows corrupting the vector table. Inspection requires reading the HardFault Status Register (HFSR) and Configurable Fault Status Register (CFSR).

Can cause an allocation (malloc or new) to fail even when total free RAM exceeds the requested size. In mission-critical 24/7 firmware, dynamic heap allocation is strictly avoided or restricted to system bootup.

Guides the compiler to place the hot/likely execution path in straight-line contiguous machine code, avoiding taken-branch instruction fetch pipeline stalls on the processor.

Defines the exact origin and length of Flash and SRAM, sets the initial stack pointer address, places the interrupt vector table at address 0x08000000 or 0x00000000, and defines memory boundaries.

Provides power-cut resilience (guarantees file system integrity even if power is lost mid-write), dynamic wear leveling across flash erase blocks, and bounded RAM/ROM footprints.

Leaf functions (functions that do not call any other functions) do not need to push LR to the stack, executing with zero stack frame memory overhead and returning via a direct BX LR instruction.

Triggered when user-level RTOS tasks attempt to execute code in SRAM (No-Execute NX violation), write to read-only Flash, or access private memory regions belonging to another task or the kernel.

Rules restrict unsafe C++ features such as implicit type conversions, raw pointers without bounds checks, unbounded recursion, unhandled enum switches, and memory leaks.

Reading or writing to a specific memory address (e.g. *(volatile uint32_t*)0x40020000) interacts directly with physical hardware pins and registers. Always requires the volatile qualifier to prevent the compiler from optimizing away repeated hardware reads/writes.

Enforces spatial isolation between RTOS tasks, prevents stack overflow from corrupting neighboring memory, and flags buffer overruns with immediate hardware MemManage exceptions.

Improperly ordered struct members cause the compiler to insert padding bytes, wasting up to 50% of SRAM. Reordering members from largest to smallest eliminates padding waste without requiring packed attributes that penalize bus performance.

Enforces error handling at compile time, preventing bugs where firmware inadvertently ignores peripheral transmission errors or sensor timeout status codes.

Allows the compiler to omit exception-handling unwinding landing pads and vector reallocation copies (enabling move-if-noexcept optimizations), significantly reducing generated code size and execution time.

In ARM Cortex-M Thumb-2 state, bit 0 of the PC must always be 1 to indicate Thumb execution mode; jumping to an address with bit 0 set to 0 triggers an immediate UsageFault (INVSTATE).

Enables object-oriented C++ classes with constructors to be instantiated inside statically allocated SRAM pools, memory-mapped peripherals, or DMA buffers with zero heap allocation.

A major source of buffer overflow vulnerabilities in embedded C/C++. Modern C++ replaces decayed arrays with std::span<T> or std::array<T, N> to preserve bounds information with zero runtime overhead.

Guarantees that hardware peripherals (SPI buses, DMA channels, interrupts) are safely closed, disabled, or unlocked even when functions exit early due to return statements or errors.

Standard library containers like std::map and std::set use node-based Red-Black trees. Each node incurs a 3-pointer + color byte overhead (24–32 bytes/node) and triggers an individual dynamic heap allocation per element, making them poorly suited for cache performance and RAM-constrained MCUs.

The gold standard for asynchronous UART/SPI communication and interrupt service routines (ISRs). Enables lock-free single-producer single-consumer (SPSC) data transfer between hardware interrupts and main processing loops without dynamic memory.

Mapped directly to non-volatile Flash ROM, consuming 0 bytes of precious SRAM. Marking lookup tables and configuration strings as const or constexpr ensures they are placed in .rodata.

Prevents double-free errors, hardware register lock leaks, and shallow-copy memory corruption when objects managing hardware peripherals or static buffers are passed or returned.

Eliminates temporary object construction, copy/move constructors, and destruction overhead, enabling large structs and buffers to be returned by value with zero runtime copy cost.

Essential in digital signal processing (DSP), motor control, and audio processing to prevent catastrophic audio clipping or motor control loop inversions. Executed in a single cycle via ARM DSP instructions (QADD, QSUB, SSAT, USAT).

ARM Cortex-M cores feature dual banked stack pointers: MSP (Main Stack Pointer, used for bootup and interrupt service routines) and PSP (Process Stack Pointer, used by user-space RTOS tasks). This dual architecture isolates task stack overflows from crashing kernel interrupt handlers.

Typically scarce in microcontrollers (ranging from 2KB on low-end MCUs to 512KB on high-end Cortex-M7). Every global variable, stack frame, and struct member must be engineered to minimize SRAM consumption.

Commonly occurs when hardware driver objects (e.g. UartDriver) attempt to log to an uninitialized console object on bootup. Solved by Meyers' Singleton (lazy initialization of a function-local static).

Provides type-safe, deterministic error handling with zero ROM overhead from exception tables and zero heap allocation, making it the preferred modern error model for embedded firmware.

Eliminates C-style array pointer decay by passing bounds information cleanly into functions, working seamlessly across C arrays, std::array, and DMA buffers with zero allocation overhead.

Allows string slicing and parsing directly over Flash ROM string literals (.rodata) or UART receive buffers without triggering dynamic heap memory allocation or copying.

Incurs zero memory overhead compared to a raw C pointer (sizeof(unique_ptr<T>) == sizeof(T*)). With custom deleters, provides automatic RAII management of hardware locks and peripheral clocks.

Provides the periodic system tick interrupt (typically configured for 1ms intervals) that drives RTOS kernel context switches, HAL_Delay() timing, and software timer callbacks.

Stored in and executed directly from non-volatile Flash ROM on microcontrollers, consuming zero SRAM space.

Delivers up to 35% better code density than pure 32-bit ARM code while maintaining full 32-bit performance, fitting complex modern firmware into constrained Flash ROM budgets.

Unlike software pseudorandom algorithms (rand() / PRNG) which repeat predictable sequences if not seeded properly, hardware TRNGs provide unpredictable random numbers essential for cryptographic keys, TLS sessions, and secure boot authentication.

Signed integer overflow, out-of-bounds pointer indexing, and strict aliasing violations allow aggressive compiler optimizations to silently eliminate critical safety checks or crash the microcontroller in unpredictable ways.

Enabling the DIV_0_TRP bit in the CCR register ensures integer division by zero triggers a deterministic hardware exception instead of returning 0 silently.

Prevents the compiler from caching register reads in CPU registers or optimizing away repeated writes. Mandatory for memory-mapped I/O (MMIO) and shared ISR flags.

Adding a single virtual method adds 4 bytes of hidden SRAM overhead per object instance on a 32-bit MCU, and indirect branch calls through function pointers prevent compiler inlining and incur pipeline bubbles.

Protects against firmware deadlocks, infinite loops, and hardware lockups in harsh EMI environments, ensuring automatic recovery in unattended systems.

NOR and NAND Flash blocks degrade after 10,000 to 100,000 erase cycles. Dynamic wear leveling rotates active data writes, while static wear leveling also periodically relocates read-only static files to equalize wear, extending hardware lifespan from months to decades.

Modern C++ features such as templates, std::string_view, std::span, constexpr, and range-based for loops compile down to the exact same or more optimal assembly instructions as hand-written C pointer arithmetic.