5.01 Function Signatures, Header Prototypes & ARM Register Passing (R0–R3)
💻 1. Annotated Source Code
#include <iostream> using namespace std; void printSomething(); void printMyName(); int main() { printSomething(); //call or invocation printMyName(); return 0; } void printSomething() { cout << "Hey! Look, I'm here!" << endl; } void printMyName() { cout << "My name is John Baugh!" << endl; }
📐 2. Architecture & UML Class Model
📚 3. Core C++ Concepts Deep-Dive
1. Forward Declarations & Prototypes
A function prototype informs the compiler of a function's name, return type, and parameter types before its definition, allowing the compiler to perform type verification and code generation across translation units.
2. Function Call Overhead
A standard function call executes a branch with link (BL) instruction, saving the return address into the Link Register (LR) and pushing caller-saved registers onto the stack.
⚡ 4. Embedded Systems & Hardware Reality
1. The ARM AAPCS Calling Convention
Under the standard ARM 32-bit calling convention (AAPCS):
- The first 4 integer/pointer arguments are passed directly in CPU hardware registers: R0, R1, R2, R3 (zero stack latency!).
- Return values are passed back in R0 (or R0-R1 for 64-bit integers).
- Arguments beyond the 4th are pushed onto the CPU stack, adding memory store and load instructions.
💡 Embedded Optimization Tip: 4-Parameter Rule
Design performance-critical functions to accept $\le 4$ parameters so all inputs reside entirely in CPU hardware registers.
💡 5. Production-Ready Embedded Refactoring
Register-friendly driver API design:
#include <cstdint> // Fits perfectly in R0, R1, R2 (Zero stack memory traffic) void configureTimer(uint8_t timer_id, uint32_t prescaler, uint32_t auto_reload) noexcept { // Direct MMIO writes using hardware registers... }
📝 Knowledge Verification Quiz
Test your understanding of the C++ concepts and embedded microcontroller trade-offs covered in this guide. Click any option for instant feedback.
STR (store) and LDR (load) memory operations.
BL (Branch with Link) instruction automatically loads the return address into the Link Register (LR / R14).